This invention relates to methods for forming semiconductor devices, and more particularly to a method for forming a self-aligned dual-oxide UMOSFET device which self-aligns a channel body doping region and its associated junction, a region for depositing the gate oxide layer, and a depth of the field layer step for a sidewall of a trench with implantation of a channel dopant at multiple-energy levels.
U.S. Pat. No. 5,637,898 describes a vertical low-voltage MOSFET construction which has a double oxide thickness along a trench sidewall and a non-uniform doping profile in the drift region. The concept of non-uniform doping profile in a drain region of a device is first described in U.S. Pat. Nos. 5,300,448 and 5,246,870, and the concept and practice of dual-oxide UMOSFET was first reported by Y. Baba et al., IEEE ISPSD symposium proceedings, p. 300,1992.
The utility of a trench UMOS device structure has been demonstrated by simulation, but attempts to fabricate the structures to achieve the performance advantage have been extremely complex, and not self-aligned.
The present invention contemplates a method for forming self-aligned dual-oxide UMOSFET which includes creating the gate by self-aligning the channel body doping region and its associated body-drift region junction, the region for depositing the gate insulating layer, and the depth of the field layer step for a sidewall of a trench with implantation of a channel dopant at multiple-energy levels.
The present invention further contemplates a self-aligned dual-oxide UMOSFET which includes a gate in the trench having a region having deposited thereon a gate insulating layer and a depth of a field layer step for a sidewall of the trench, both of which are self-aligned with the alignment and formation of the channel body doping region and the body-drift region junction through implantation of a channel dopant at multiple-energy levels.